With the improvement of the performance of information processors such as communication apparatus and servers, the speed at which signals are transmitted and received inside and outside the information processors has increased.
With the improvement of transmission speed, signal waveforms attenuate due to frequency-dependent loss. As a result, inter-symbol interference (ISI) occurs and bit error rates degrade. Accordingly, equalizers which suppress ISI are used in receiver circuits.
A decision feedback equalizer (DFE) which equalizes an input signal according to past data is one of equalizers which suppress ISI.
A DFE which generates two filter patterns that differ by only one bit, which determines the magnitude of ISI by finding the difference between received waveforms at the time of a received data string matching the two filter patterns, and which adjusts equalization intensity on the basis of the magnitude of the ISI is proposed. With this DFE the difference between two received waveforms which match the two filter patterns, at the time of data of a bit one bit after the bit by which the two filter patterns differ being received, is found. By doing so, the magnitude of ISI caused by the bit (by which the two filter patterns differ) one bit before this bit is observed.
U.S. Pat. No. 8,503,519
Japanese Laid-open Patent Publication No. 2012-170078
Japanese Laid-open Patent Publication No. 2012-170079
Japanese Laid-open Patent Publication No. 2012-170081
Japanese Laid-open Patent Publication No. 2009-225018
By the way, each tap in a DFE reproduces ISI during each unit interval (UI), so a plurality of taps are used for curbing the influence of ISI during plural UIs. In that case, a circuit which adjusts a tap coefficient (equalization coefficient) is arranged for each tap. This increases circuit area.